The present invention relates generally to the fabrication of complementary metal-oxide-semiconductor integrated circuits (ICs), and more particularly to the implementation of divided drain implants to enhance IC electrostatic discharge protection while simplifying the IC fabrication process.
As device dimensions continue to be reduced, susceptibility to electrostatic discharge (ESD) damage is a growing concern. ESD events occur when a charge is transferred between one or more pins of an integrated circuit (IC) and another conducting object in a short period of time, typically less than one microsecond. The rapid charge transfer generates voltages large enough to breakdown insulating films, such as silicon dioxide, and to cause permanent damage to the device. To deal with the problem of ESD events, IC manufacturers have designed various structures on the input and output pads of their devices to shunt ESD currents away from sensitive internal structures. However, these additional ESD protection structures typically require additional masks and processes to implement into the IC, which increases the fabrication process time and cost.
Therefore, desirable in the art of CMOS IC ESD protection designs are improved ESD protection structures that can be implemented on both N type and P type CMOS devices without additional masks to minimize the IC fabrication process time and costs while increasing CMOS IC ESD protection.